The yield of an IC is a critical factor for the commercial success of the IC. Achieving high and stable yields helps ensure that products meet quality and reliability objectives and are profitable in the market place. When a new manufacturing process is introduced, or a new product is introduced to a mature manufacturing process, yields tend to be significantly lower than acceptable. The ability to meet profitability and quality objectives, and perhaps more importantly, time-to-market and time-to-volume objectives depend greatly on the rate at which the low yield can be ramped up. The yield ramp process can be speeded up by yield learning or analysis.
Some yield analysis techniques extract information about failure mechanisms causing yield loss from volume scan diagnosis results. Scan diagnosis is a process that can identify specific locations in a design that are likely to explain failing scan test data. Results produced by a scan diagnosis process usually are not definite. The ambiguity is two-fold: First, the scan diagnosis often identifies multiple locations (referred to as suspects hereinafter) for observed defective logical behavior; second, each suspect may be associated with multiple possible root causes.
Statistical methods based on aggregation of raw diagnosis results have been developed to derive the root cause distribution information. These methods can identify root causes associated with bridge defects but do not deal with or have difficulties in dealing with metal open defects. One of the reasons may be the correlation among metal layers and via in the diagnostic callouts. Moreover, many of these yield learning methods employ iterative learning algorithms but could not avoid over-fitting problems. This is of real practical concern as the number of possible root causes can be on the order of hundreds or thousands and in some case significantly outnumber the total number of failing devices being analyzed. Therefore, yield analysis methods that can overcome the above limitations are desirable.